The team, led by Professor Takayuki Kawahara, showcased a processor that overcomes these limitations by distributing calculations across multiple LSI chips. This innovation was detailed in an IEEE Access study published on January 30, 2024, and further presented at the IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics (SAMI 2024) on January 25, 2024.
Prof. Kawahara's team's goal is to facilitate advanced information processing directly at the edge, leveraging a unique processing architecture. The team developed a fully coupled LSI on a single chip using 28nm CMOS technology and introduced a scalable approach with parallel-operating chips, demonstrating its effectiveness using FPGAs in 2022.
The scalable annealing processor utilizes 36 22nm CMOS calculation LSI chips and one control FPGA, capable of constructing large-scale semiconductor systems with 4096 spins, following the Ising model. This model is crucial for understanding magnetic systems. The processor's design reduces chip requirements by about half and operates with modest power needs, significantly outperforming traditional computing methods in power performance ratio.
Professor Kawahara envisions broad social implementation of this technology, including business ventures, joint research, and technology transfer. He aims to develop an LSI system by 2030 that rivals the computing power of a 2050-level quantum computer for combinatorial optimization problems, all without the need for extensive infrastructure.
This development not only represents a leap forward in semiconductor technology but also paves the way for new digital industries, highlighting the Tokyo University of Science's leading role in technological innovation.
Research Report:Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI
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